As the size of integrated circuit features on integrated circuit chips become smaller and the density of devices on integrated circuit chips increases, e.g., to increase device speed, new problems arise in scaling down the devices and interconnections. The size of conductive vias and contacts typically scale down to match the scaling down of other components and devices on integrated circuit chips. The minimum cross-section area of a via plug or contact plug is important to ensure that the via or contact does not have too much resistance to current flow. As used herein, the term “plug” is used broadly enough to include a conventional plug structure, as well as a structure formed using damascene and/or dual damascene processes.
FIG. 1 is a cross-section view of a via plug 20 formed using current processes. A buffer layer 22 is formed on an underlying layer 24 and a dielectric layer 26 is formed on the buffer layer 22. This buffer layer 22 may be an etch stop layer, for example. The via plug 20 in FIG. 1 is electrically connected to a conductive line 28 (e.g., copper line) in an underlying layer 24. The via hole 30 of FIG. 1 has a reduced cross-section area where it opens to the underlying layer 24 at the buffer layer 22. Using conventional methods of forming a via hole, often an anisotropic etch of the buffer layer 22 or etch stop layer is performed to provide a smooth slope for the via hole profile. Although this smooth slope may be desirable for other processing reasons (e.g., maintaining critical dimensions for upper portion of via hole, more uniform coverage of hole surfaces by barrier layer using PVD), etc., the reduced cross-section area at the buffer layer 22 will cause increased electrical resistance through the via plug 20.
FIG. 2 is a cross-section view showing a contact hole 32 formed between two transistors 34 and opening to a source/drain region 36. The transistors 34 have a buffer layer 22 formed over them, and the buffer layer 22 is covered by a dielectric layer 26. The buffer layer 22 of FIG. 2 has tensile stress to induce compressive strain on the channel regions 38 of the transistors 34 there below. When etching the contact hole 32 using conventional methods (e.g., anisotropic etch of buffer layer 22), the cross-section area of the contact hole 32 becomes smaller at the buffer layer 22. And in FIG. 2, the cross-section area of the contact hole 32 is smallest where it opens to the underlying layer 24 (which in this case is the substrate wherein source/drain region 36 is formed) due to the tapered profile of the contact hole 32 at the buffer layer 22. The negative effects of this tapering in the buffer layer 22 of FIG. 2 are not great because the buffer layer 22 is not thicker. However, it is often desirable to have a thicker buffer layer 22 for inducing strain on the channel regions 38 of the transistors 34.
But as shown in FIG. 3, if the buffer layer thickness is increased, then the cross-section area of the contact hole 32 where it opens to the underlying layer 24 at the buffer layer 22 becomes smaller. Note that the size H of the contact hole opening at the underlying layer 24 in FIG. 2 is much larger than that of FIG. 3. The tapering effect in the buffer layer 22 created using conventional hole formation methods may preclude the use of thicker buffer layers 22. Hence, there is a need for an improved via hole or contact hole structure and a corresponding method of forming the same, that will allow for thicker buffer layers to be used and that will prevent the increase in resistance through a via or contact plug as the overall cross-section areas of such plugs continue to shrink to meet current production demands (e.g., as device dimensions shrink and as device density increases on a chip).